The present invention relates generally to the field of detector circuitry for imaging systems and the like. More particularly, the invention relates to a technique for compensating for parasitic capacitance in a detector circuit, such as a digital pixel array circuit used in x-ray imaging systems.
Various techniques are known and are presently in use for providing images of subjects of interest. For example, in the medical imaging field, x-ray techniques have long been employed to provide useful images of anatomy within a patient. In conventional x-ray techniques, radiation is emitted through a subject and allowed to impact a photographic film which captures the desired image. The film is then processed to provide contrast between features of interest. Recently, digital x-ray techniques have been developed which permit images to be captured and processed digitally, saved in digital form, transmitted, reprinted, and so forth.
The advent of digital imaging systems, particularly x-ray systems, has raised an array of problems, particularly in the design and operation of the data acquisition circuitry. In digital x-ray systems, for example, a detector is employed to generate signals which arc representative of an amount or intensity of radiation striking individual picture elements, or pixels of a detector surface. During the data acquisition sequence, circuitry within the detector is sequentially scanned to capture the resulting signals. The signals can then be processed to obtain useful image data which is subsequently used to reconstruct the desired image. The images are then displayed on computer monitors, stored on conventional photographic film, and so forth, for use by attending physicians and radiologists.
In one type of digital x-ray detector rows and columns of detector elements generate signals in response to photons impacting a scintillator. Each element consists of a photo diode and a thin film transistor. The cathode of the diode is connected to the source of the transistor, and the anodes of all diodes are connected to a negative bias voltage. The gates of the transistors in a row are connected together and the row electrode is connected to scanning electronics. The drains of the transistors in each column are connected together and each column electrode is connected to additional readout electronics. Sequential scanning of the rows and columns permits the system to acquire the entire array or matrix of signals for subsequent signal processing and display.
In digital detectors of the type described above, problems arise due to parasitic capacitance between the columns and rows. In general, when the row control voltage is changed from an xe2x80x9coffxe2x80x9d voltage to an xe2x80x9conxe2x80x9d voltage, parasitic capacitance between each row and every column causes some charge to be measured at the column electrode. This voltage can cause false readings, saturate sensing circuitry, and cause anomalies in resulting image data. These, in turn, can result in undesirable image artifacts.
Techniques have been developed to compensate for such parasitic capacitance. In one known technique, for example, the charge on a column is balanced by a compensation voltage applied to rows other than the row or rows being enabled. Moreover, the number of rows to which the compensation voltage is applied can be altered, or the compensation voltage itself can be altered to provide the necessary degree of balancing.
While the foregoing technique provides generally satisfactory results, it is not without drawbacks. For example, depending upon the scanning mode employed with the detector, single or multiple rows may be scanned at one time. Moreover, where multiple rows are scanned simultaneously, different scanning modes may call for different numbers of rows to be scanned. Existing compensation techniques are not well suited to such multiple modes of scanning. While the techniques could employ different compensation voltages for the different scanning modes, depending upon the number of rows being scanned simultaneously, such adaptations result in more complicated analog bias circuitry, and could call for compensation voltage levels which may be higher than desired design limits.
There is a need, therefore, for an improved technique for compensating for capacitive coupling in digital detector circuits which facilitates multiple scanning modes. Moreover, there is a need for an improved compensation scheme which permits single or multiple row scan modes, while enabling a single, uniform compensation voltage to be employed in each of the different modes.
The invention provides a novel voltage compensation technique for digital detectors designed to respond to these needs. The technique may be employed in a variety of devices, and is particularly well suited for implementation in a digital x-ray detector. The technique provides for a number of different scanning modes, such as single, double, or multiple row scanning, such as for scanning 16 or 32 rows in the detector at once. Depending upon the particular scanning mode, a different number of rows are biased to a compensation voltage, thereby compensating for or balancing charges due to parasitic capacitance between rows and columns. The technique may be used in detectors having a variety of row and column sampling or scanning configurations. Similarly, the technique may be employed in scanners having various pixel matrix dimensions. The technique therefore accommodates demanding scanning scenarios in which a large number of rows must be compensated, while permitting a fewer number of rows to be compensated in less demanding scanning modes.
Thus, in accordance with a first aspect of the invention, a method for scanning image data in a discrete pixel detector is provided. The detector is of the type having a plurality of rows and a plurality of columns arranged in an image matrix. In accordance with the method, reading of image data from the rows is sequentially enabled in one of a plurality of scan modes. In each of the scan modes, a different number of rows is enabled. For each sequential row enabling step, a compensation voltage is applied to a group of other rows. The compensation voltage is the same for each of the different scan modes. Accordingly, a different number of rows receives the compensation voltage in each of the scan modes. For each sequential row enabling step, image data is then read from each column of the detector.
The compensation voltage is conveniently determined by reference to the most demanding scan mode, that is, wherein a maximum number of rows is scanned. Thereafter, a single compensation voltage may be applied for compensation of parasitic capacitance charges, with the number of rows receiving the compensation voltage proportionally the same with respect to the number of enabled rows in each scan mode. The compensation voltage may be determined based upon such factors as the enabled rows/compensating rows ratio, a threshold voltage, an enabling voltage, an xe2x80x9coffxe2x80x9d or disabled voltage and anticipated or actual values of parasitic capacitance.
The invention also provides a method for compensating charges in a discrete pixel detector wherein a maximum number of rows to be enabled during any one of a plurality of scan modes is determined, as is a desired maximum number of rows to be used for the charge compensation when the maximum enabled rows are occupied. The desired compensation voltage is then determined based upon the maximum number of enabled rows and the number of rows to be used for compensation. Once this compensation voltage is established, the number of compensating rows may be determined for each of the plurality of scan modes. Again, the ratio between the number of enabled rows and the number of compensating rows may remain constant throughout the various scan modes.
The invention also provides a detector system adapted for implementing the charge compensation techniques. The detector system includes circuitry for enabling rows, as well as circuitry for applying compensation voltages to a number of rows during each enabling step. The circuitry thereby permits a single compensation voltage to be used for charge compensation independent of the number of rows being enabled at any one time.